Say the FPGA chip counted 180 steps between encoder increments. Dividing 180 by four yields 45, so between the next two decoder valve changes, we waited 45 cycles and incremented a 2-bit count, waited another 45 cycles and incremented the count again, and so on. We reset the 2-bit counter and performed the division again after each encoder increment to keep the piston synchronized with any change in the valve's speed.